Cost analysis of a new algorithmic-based soft-error tolerant architecture

A new ABFT architecture is proposed to tolerate multiple soft-errors with low overheads. It memorizes operands on a stack upon error detection and corrects errors by recomputing. This allows uninterrupted input data streams to be processed without data loss. Several methods based on physical, electrical or logical principles have been proposed to reduce the susceptibility to error in digital systems. A system-level method, called Algorithmic-Based Fault Tolerance (ABFT), was originally proposed to obtain fault-tolerant processor array systems 1]. ABFT is a concurrent error detection/correction technique with relatively low hardware and time redundancy. This method operates on encoded input data sets and produces encoded output data. This on-line fault-tolerance scheme was successfully applied to many applications, such as Fourier Transform 2, 3, 4, 5, 6] and solving matrix equations 7, 8, 9, 10]. Some theoretical ABFT hardware and time overhead bounds have been published by several authors 11, 10, 8]. However, in practice, it can easily be shown that hardware and time overhead for ABFT can become totally unacceptable when multiple errors must be tolerated. Moreover, existing ABFT architectures interrupt the input data stream at each detected error, because they use the processing elements to recompute the results on detected errors. This interruption can be relatively long and undesirable in real-time applications. This paper begins by showing the limitations of ABFT in simple computational systems designed to tolerate soft-errors. Soft-errors are deened as temporary and non-recurring errors. A source of soft-errors is the so-called Single Event Upsets, SEU 12]. The structure of a new algorithm based soft-error tolerant architecture for real-time applications is then presented. It uses mainly two new techniques to allow uninterrupted input data streams to be processed without data loss when subject to soft-error. Firstly, it uses a memory map for results, which reduces the time overhead by dividing the computational part from the error detection/correction part. Secondly, to obtain low overheads, it exploits the very high error coverage ooered by the detection mechanisms of simple encoding schemes. This system uses a stack, and allows nearly continuous processing of input data streams, without interruption on detected error. The proposed architecture was brieey introduced